library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_signed.all;
use ieee.numeric_std.all;

entity sound_module is
	port (clk, reset: in std_logic;
		enable: in std_logic;
		freqdiv: in std_logic_vector (31 downto 0);
		audio_l, audio_r: out std_logic
		);
end sound_module;

architecture RTL of sound_module is
	signal counter: std_logic_vector (23 downto 0);
	signal audio_out: std_logic := '0';
begin
	audio_l <= not audio_out; -- Optimierung
	audio_r <= not audio_out;
	
	process (clk, reset, enable, freqdiv, counter, audio_out)	
		
	begin		
		if rising_edge(clk) then
			if reset = '1' then
				counter <= conv_std_logic_vector (0, 24);
				audio_out <= '0';
			elsif enable = '1' then 
				counter <= counter - 1;
				if counter < 0 then
					counter <= freqdiv(23 downto 0);
					audio_out <= not audio_out;		
				end if;
			end if;		
		end if;
	end process;
end RTL;

